Memory devices, including a synchronous dynamic random access memory Double Data Rate 10 shown in FIG. 1, typically receive both a row address and a column address that specify where data are to be transferred to or from within the memory device. The row and column addresses are initially applied to an address register 12 through an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20, 22 depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 20, 22 is a respective row address latch 26 that stores the row address, and a row decoder 28 that applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20, 22. The row addresses are generated for refresh purposes by a refresh counter 30 that is controlled by a refresh controller 32.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. In a normal operating mode, the column address is coupled through a burst controller 42 directly to an address buffer 44. However, in a burst operating mode, the burst controller 42 generates a sequence of column addresses starting at the column address applied to the burst controller 42 from the column address latch 40. For example, the burst controller 42 may operate in a “burst 2” mode, in which one additional column address is generated by the burst controller 42, a “burst 4” mode, in which three additional column addresses are generated by the burst controller 42, and a “burst 8” mode, in which seven additional column addresses are generated by the burst controller 42. The burst controller 42 may also operate in either of two burst modes, namely a serial mode, in which the addresses generated by the burst controller 42 are sequential, or an interleaved mode, in which the addresses generated by the burst controller are sequential except that only the least significant bitt toggles between each pair of even and odd addresses. As discussed in greater detail below, it is important that column addresses generated by the burst controller 42 be quickly coupled to the column address buffer 44 after the burst controller 42 receives the initial column address from the column address latch 40.
After the burst controller 42 applies a column address to the column address buffer 44 in either the normal mode or the burst mode, the column address buffer 44 applies the column address to a column decoder 48. As is well known in the art, the column decoder 48 applies various signals to respective sense amplifiers and associated column circuitry 50, 52 for the respective arrays 20, 22.
Data to be read from one of the arrays 20, 22 is coupled to the column circuitry 50, 52 for the arrays 20, 22, respectively. The data are then coupled to a data output register 56, which applies the data to a data bus 58. Data to be written to one of the arrays 20, 22 are coupled from the data bus 58 through a data input register 60 to the column circuitry 50, 52 where they are transferred to the arrays 20, 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuitry 50, 52, such as by selectively masking data to be read from the arrays 20, 22.
The above-described operation of the Double Data Rate 10 is controlled by a command decoder 68 responsive to high-level command signals received on a control bus 70. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. The command decoder 68 generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by the command signals. These control signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. The high-level command signals are clocked into the command decoder 68 in synchronism with a clock signal CLK. The CLK signal, or internal clock signals (not shown) generated from the CLK signal, control the timing at which the control signals carry out their respective functions in the SDRAM 10. The control signals are preferably registered with both the rising and falling edges of the CLK signal (or internal clock signals) so that two operations are accomplished each period of the CLK signal. An SDRAM 10 operating in this manner is known as a “Double Data Rate DRAM” because two bits of data are read from or written to the SDRAM 10 for each clock CLK pulse.
One conventional design for a portion of the burst controller 42 is illustrated in FIG. 2. The burst controller 42′ may include substantially more circuitry than is shown in FIG. 2, but this circuitry has been omitted in the interest of brevity because this additional circuitry is not particularly relevant to the problem that the disclosed invention is intended to solve. The signals XA0-XA9 are the external column address signals coupled to the SDRAM 10 through the address bus 14 (FIG. 1) and then through the address register 12 to the column address latch 40. As previously mentioned, the burst controller 42′ then outputs column address designated as IA0-IA9 to the column address buffer 44. In the burst mode, bits IA0 and IA3-IA9 of the internal column address are generated differently from the remaining bits IA1 and IA2 of the internal column address. More specifically, the IA0 and IA3-IA9 bits are generated by coupling the external bits A0 and A3-A9 from respective column address latches 40 through a respective column address path 90. The reason these bits are generated differently is that the maximum size of the burst is 8 bits, and 8 bits can be counted using three bits of the internal address, i.e., IA2, IA1 and IA0. The bits IA3-IA9 of the internal column address are constant as the IA2-IA0 bits are incremented by a count of either 2, 4 or 8, depending upon the length of the burst. The IA0 bit selects whether an even or an odd-numbered column will be initially addressed, and it toggles with each edge of the CLK signal, assuming the SDRAM 10 is a double data rate SDRAM.
As mentioned above, in the burst mode, the IA2 and IA1 bits are incremented from their initial values. This incrementing is accomplished for the first bit of the burst by adder logic circuits 100 and 102. The adder logic circuit 100 receives a latched external address bits LA_S0 and LA_S1 from respective column address latches 40. The adder logic circuit 102 receives latched external address bits LA_S0, LA_S1 and LA_S2 from respective column address latches 40. The adder logic circuits 100, 102 then output respective address bits A1_INC and A2_INC, which are applied to an input of a respective multiplexer 110, 112. The other input of each multiplexer receives a respective set of bits from a burst counter 116. The burst counter 116 supplies the bits CNT1_INC and CNT2_INC for all column addresses of a burst after the first bit of the burst. Each multiplexer 110, 112 is controlled by a RDWRA signal that has a first logic level during the first bit of a burst and has a second logic level during the remaining bits of the burst. The multiplexers 110, 112 thus couple the input of respective drivers 120, 122 to the outputs of respective adder logic circuits 100, 102 during the first bit of a burst, and then to the burst counter 116 during the remaining bits of the burst. The drivers 120, 122, as well as a set of drivers 128 coupled to the outputs of the column address path 90, output the resulting bits IA0-IA9 to the column decoder 48 (FIG. 1).
As previously mentioned, the columns in the memory banks 20, 22 are divided into even-numbered and odd-numbered columns. As will be explained further below, the IA2 and IA1 bits of each column address for the odd-numbered columns (in which the IA0 bit is a “1”) in the first bit of each burst are generated directly from the XA2 and XA1 bits so that IA2=XA2 and IA1=XA1. The IA2 and IA1 bits of each column addresses for the even-numbered columns (in which the IA0 bit is a “0”) in the first bit of each burst are generated by the adder logic circuits 100, 102.
Several examples of the low-order bits IA2, IA1 of the internal address generated from the low-order bits XA2, XA1, XA0 of the external address for several different burst operating modes will now be provided. The first example shows the internal addresses generated for a burst of 8 starting with address “010” in a serial column access. The low-order bits of the external address and the IA2 and IA1 bits of the internal address bits are as follows:
External AddressesXA2XA1XA0010Internal AddressesIA2IA1First bit of burst010Even011OddSecond bit of burst100Even101OddThird bit of burst110Even111OddLast bit of burst000Even001Odd
In this case, since the low-order bit XA0 is “0”, the internal address bits IA2 and IA1 for both the even-numbered column and the odd-numbered column are the same as respective external address bits XA2 and XA1. For the first bit of the burst, the internal address bits IA2 and IA1 for the even-numbered column are generated by the adder logic circuits 100, 102, and the internal address bits IA2 and IA1 for the odd-numbered column are generated directly from the external address bits XA2 and XA1, respectively. For the second through last bits of the burst, the internal address bits IA2 and IA1 for both the even-numbered columns are generated by the burst counter 116.
In a second example, a burst of 8 in a serial column access occurs starting with address “011”. The IA2 and IA1 bits of the internal address bits are as follows:
External AddressesXA2XA1XA0011Internal AddressesIA2IA1First bit of burst011Odd100EvenSecond bit of burst101Odd110EvenThird bit of burst111Odd000EvenLast bit of burst001Odd010Even
In this case, since the low-order bit XA0 is “1” and the burst mode is for a serial address with a burst of 8, the internal address bits IA2 and IA1 for the even-numbered column are the complement of the respective external address bits XA2 and XA1.
The third example is for serial access with a burst length of 4, starting at address “010”.
External AddressesXA2XA1XA0010Internal AddressesIA2IA1First bit of burst010Even011OddLast bit of burst000Even001Odd
In this case, IA2 does not change since, for a burst length of 4, only IA1 must change to count to 4. Since XA0 is “0”, IA0 for the even-numbered column address is equal to XA0.
The fourth example is also for a serial access with a burst length of 4, but this time the initial column address is “011”.
External AddressesXA2XA1XA0011Internal AddressesIA2IA1First bit of burst011Odd000EvenLast bit of burst001Odd010Even
Again, since a burst length of 4 only requires that the address be increment by 4, IA2 does not change. However, since XA0 is equal to “1”, IA1 for the even-numbered column address is equal to the complement of XA1.
In a fifth example, a burst length of 2 occurs with a serial access and a starting address of “010”.
External AddressesXA2XA1XA0010Internal AddressesIA2IA1First bit of burst010Even011Odd
In this case, neither IA2 nor IA1 change since, for a count of 2, only IA0 must change. Since XA0 is “0”, IA0 for the even-numbered column address is equal to XA0.
A sixth example also uses a burst length of 2 with a serial access, but this time the starting address is “011”.
External AddressesXA2XA1XA0011Internal AddressesIA2IA1First bit of burst011Odd010Even
Again, neither IA2 nor IA1 change since, for a count of 2, only IA0 must change. But since XA0 is “1”, IA0 for the even-numbered column address is equal to the complement of XA0.
In a seventh example, an interleaved access occurs with a burst length of 8, starting at a column address “010”.
External AddressesXA2XA1XA0010Internal AddressesIA2IA1First bit of burst010Even011OddSecond bit of burst100Even101OddThird bit of burst110Even111OddLast bit of burst000Even001Odd
In this case, the internal address bits IA2 and IA1 for both the even-numbered column and the odd-numbered column are the same as respective external address bits XA2 and XA1. Thus, for a burst length of 8 when XA0 is “0”, IA2 and IA1 have the same relationship to XA2 and XA1, respectively, in both the serial access mode and the interleaved access mode.
A final example is for an interleaved access with a burst length of 8 and a starting column address of “011”.
External AddressesXA2XA1XA0011Internal AddressesIA2IA1First bit of burst011Odd010EvenSecond bit of burst101Odd100EvenThird bit of burst111Odd110EvenLast bit of burst001Odd000EvenIn this case, the internal address bits IA2 and IA1 for the even-numbered column are the same as respective external address bits XA2 and XA1. Thus, for a burst length of 8 when XA0 is “1”, IA2 and IA1 have the opposite relationship to XA2 and XA1, respectively, in the interleaved access mode than they have in the serial access mode, as will be apparent by comparing this example to example 1.
Based on the forgoing, and other examples that can be given, it can be seen that IA2 and IA1 for the even column addresses are the following functions of XA2, XA1 and XA0 (“*” denotes an “and” function and “+” denotes an “or” function):                for IA1IA1=XA1 for XA0=“0”+Burst2+InterleaveIA1=XA1* for XA0=“1”*Burst8 or 4*Serialfor IA2IA2=XA2 for XA0=“0”+XA1=“0”+Burst2 or 4+InterleaveIA2=XA2* for XA0=“1”* XA1=“1”* and Burst8*Serial        
As explained below, the adder logic circuits 100, 102 implement the above equations to determine the IA1 and IA2 bits of the column address for the even-numbered columns for the first bit of each burst.
The burst controller 42′ is shown in greater detail in FIG. 3. The adder logic circuit 100 for the XA1 bit receives the latched address bits signal LA_S0 and LA_S1 from respective column address latches 40, as previously explained. The LA_S1 signal is coupled through an inverter 140 to one input of a multiplexer 142 while a second input of the multiplexer 142 receives its complement through an inverter 146. The multiplexer 142 outputs a signal to an inverter 146 that corresponds to either the XA1 bit or its complement depending upon the state of a signal applied to the CLK input of the multiplexer 142. The CLK input of the multiplexer 142 is driven by a NOR-gate 150, which receives the complement of the latched LA_S0 signal from an inverter 152. If the output of the NOR-gate 150 is low, the multiplexer 142 couples the output of the inverter 140 to the input of the inverter 146. The output of the NOR-gate 150 will be low whenever the complement of the LA_S0 signal is high, which will occur whenever the external address input XA0 is low. The output of the NOR-gate 150 will also be low whenever a BURST2 input is high, which occurs in the burst 2 mode. Finally, a LINTL signal will be high whenever the burst controller 42′ is operating in the interleaved mode. Thus, the NOR-gate 150 and the inverter 152 cause the multiplexer 142 to output the complement of the LA_S1 signal in the either the burst 2 mode, when the latched external input LA_S0 is low or in the interleaved mode. The LA_S1 signal is inverted twice, once by the inverter 140 and once by the inverter 146 as it is coupled through the multiplexer 142 to the output as signal A1_INC. The A1_INC signal will thus be equal to the LA_S1 signal in either the burst 2 or interleaved modes, or when the external address bit XA0 is low. In all other situations, i.e. in the either the burst 4 or burst 8 modes and when the external address bit XA0 is low, the multiplexer 142 outputs the LA_S1 signal, thus making the A1_INC signal equal to the complement of the LA_S1 signal.
The adder logic circuit 102 for the IA2 bit operates in a manner similar to the operation of the adder logic circuit 100. Specifically, the latched external address bit LA_S2 is applied to one input of a multiplexer 162 through two inverters 160, 164, and the complement of the LA_S2 bit is applied to another input of the multiplexer 162 through the inverter 160. A NOR-gate 170 is coupled to the CLK input of the multiplexer 162, and input so the NOR-gate 170 are coupled to outputs from a NAND-gate 172 and inverter 174. The NOR-gate 170, NAND-gate 172 and inverter 174 decode the latched LA_S0 and LA_S1 bits, a burst 8 signal indicative of operation in the burst 8 mode and the LINTL signal indicative of operation in the interleaved mode. The signals are decoded so that the multiplexer 162 couples the output of the inverter 160 to an inverter 178, thus making the A2_INC signal equal to the LA_S2 bit when the burst controller 42′ is operating in either the burst 8 or at the interleaved mode or when the external address bit XA0 is 0. When the burst controller 42′ is operating in the burst 8 mode and the serial mode, and when the XA0 and XA1 bits are both 1, the multiplexer 162 couples the output of the inverter 164 to its output, thus making the A2_INC signal equal to the complement of the LA_S2 bit.
The output of the adder logic circuit 100 is applied to one input of the multiplexer 110. The other input of the multiplexer 110 receives a CNT1_INC signal from the burst counter 116 (FIG. 2), as previously explained. During the first bit of a burst, the RDWRA signal is high to cause the multiplexer 110 to couple the A1_INC input to the output, thus making the internal address bit IA1 for the even column equal to the A1_INC signal. For subsequent bits of the burst, the RDWRA signal is low to cause the multiplexer 110 to couple the CNT1_INC input to the output, thus making the internal address bit IA1 for the even column equal to the CNT1_INC signal. The output of the adder logic circuit 102 is coupled through the multiplexer 112 in essentially the same manner.
In summary, the above-described circuitry of the burst controller 42′ functions to make the internal address bit IA1 equal to the external address bit XA1 when the burst controller 42′ is operating in the burst 2 mode or the interleaved mode or when the external address bit XA0 is “0”. The internal address bit IA1 is equal to the complement of the external address bit XA1 when the burst controller 42′ is operating in the interleaved mode and in either the burst 4 or 8 mode and the external address bit XA0 is “1”. Similarly, the above-described circuitry functions to make the IA2 bit equal to the external address bit XA2 when the burst controller 42′ is operating in the burst 2 or burst 4 mode or the interleaved mode or when the XA0 bit is “0” or the XA1 bit is “0”. The internal address bit IA2 is equal to the complement of the external address bit XA2 when the burst controller 42′ is operating in the serial mode and in the burst 8 mode and the external address bits XA0 and XA1 are both “1”.
The major disadvantage of the circuitry used in the burst controller 42′ of FIGS. 2 and 3 stems from the number of circuit components the external address bits must be coupled through to generate the internal address bits. Specifically, from the address latch 40, the LA_S0 signal for the even columns is coupled through the inverter 152, the NOR-gate 150, the multiplexer 142, the inverter 146, and the multiplexer 110. In contrast, the LA_S0 signal for the odd columns is coupled through only a multiplexer 170. A similar disparity exists between the LA_S1 signal for the odd columns and the LA_S1 signal for the even columns. As a result, the internal address bits IA1 and IA2 for the even columns reach the column decoder 44 (FIG. 1) substantially later than the internal address bits IA1 and IA2 for the odd columns. In addition to this lack of symmetry, the inherent delay in passing the latched address bits LA_S0 and LA_S1 through 5 circuit components unduly delays the time that the column decoder 44 can begin decoding a column address.
As the speed at which memory devices continues to increase, these delays in decoding, addresses can markedly slow the operating speed of memory devices. There is therefore need for a burst controller that is capable of outputting internal addresses with less delay than the prior art burst controller described above.